DirAc: An Integrated Circuit for Direct Acquisition of the M-Code Signal

This paper describes the first integrated circuit (IC) designed, fabricated, and tested to perform direct acquisition of the M code signal. This DirAc IC prototype provides direct acquisition capability for test receivers and also demonstrates the feasibility of performing direct acquisition over extended regions of time and frequency uncertainty. The IC is designed and fabricated using 180 nm technology, and has been tested to demonstrate complete functionality and full performance. It uses parallel code matched filters, with FFT-based backend processing to search over 800 Hz of frequency uncertainty and 10 msec of time uncertainty in parallel, using off-chip memory for noncoherent integration. Multiple such timefrequency tiles are searched serially. Inputs are sampled at 2 bits each inphase and quadraphase. The DirAc IC supports a maximum integration time (combined coherent and noncoherent integration) of 1.28 seconds, and includes compensation for code Doppler. Coherent integration time up to 10 msec can be used. The DirAc IC’s architecture takes advantage of the M-code signal’s binary offset carrier (BOC) modulation to reduce acquisition processing complexity. DirAc supports different modes and features of the M-code signal. Hardware is time-shared between inphase and quadraphase processing and also between upper and lower sidebands of the BOC modulation. The architecture uses a pipelined design to provide the equivalent processing capability of 3.2 million parallel correlators, performing 2 tera operations per second. Average power consumption in a typical application is less than 1 mW. The IC design and layout process are also described, identifying techniques used to efficiently design and layout the IC. Theoretical predictions are provided for search speed and for the ability to work at different levels of carrier-to-noise density ratio. INTRODUCTION The M-code signal, the modernized GPS military signal designed in the late 1990s, is scheduled to be first transmitted by a Block IIR-M satellite in 2005. As described in [1], the M-code signal’s revolutionary design includes a novel modulation [2], new data message, and new security architecture. M-code signal acquisition relies primarily upon direct acquisition, where in effect the receiver correlates (over time and frequency shifts) a locally generated replica of an M-code signal with the received waveform. When there is a match between the replica and a received signal, coarse synchronization is achieved, and the receiver commences signal tracking, data message demodulation, and position calculation. Since the M-code signal, like the current GPS military signal called Y-code signal, uses very long spreading codes, signal acquisition cannot take advantage of the short spreading codes that simplify acquisition processing in civilian signals such as the GPS C/A-code signal. While direct acquisition circuits were developed for Y code receivers in the 1990s [3], these circuits provided much less capability than would be needed for direct acquisition to be the primary mechanism for acquiring the M-code signal. During the design of the M-code signal, studies demonstrated that a combination of factors would allow direct acquisition to surpass the design requirements for the M-code signal. But the results of these studies did not lead to consensus that ICs ready for receiver production in the latter half of this decade could meet the performance requirements while providing adequately low complexity, low parts cost, low peak and average power consumption, and low thermal dissipation. Functioning silicon was needed to remove remaining doubts. A team with expertise in systems engineering, digital signal processing, and IC design took on the challenge of developing a prototype IC for direct acquisition of the Mcode signal. The team identified ways to exploit the unique characteristics of the M-code signal, evaluated processing architectures that balanced risk and capability, developed predictions of performance and of IC complexity, designed and applied algorithms, developed detailed simulations, and traded off processing implementations, yielding design files that were sent to the foundry only 12 calendar months after the design effort began. The resulting “DirAc” ICs have been packaged and tested, confirming that they provide full functionality and meet or exceed performance predictions. Software and hardware development is underway to integrate the IC into a test receiver for further testing. The next section of this paper discusses direct acquisition of the M-code signal, outlining issues and opportunities to be considered. The following section describes the DirAc architecture. The subsequent section describes the first DirAc IC’s design, including digital signal processing, architecture, and layout, built using 180 nm lithography readily accessible in 2001. The succeeding section outlines a second version DirAc that could be developed using 130 nm technology available in 2003. Fundamental performance characteristics are provided in the subsequent section, while the final section summarizes the findings of this paper. DIRECT ACQUISITION OF THE M-CODE SIGNAL Signal acquisition involves the steps that take a receiver from a state of being powered on and having passed selftest, to providing an initial estimate of position, time, or velocity (PVT) at specified accuracy. Time to first fix (TTFF) denotes the delay between starting the acquisition process and providing PVT with specified accuracy. In conventional receivers, TTFF then involves the time for coarse initial synchronization (obtaining initial alignment between the receiver’s timing and frequency and those of the received signal), signal tracking or other processing that produces refined and repeated estimates of signal timing and frequency, reading the data message to obtain position and time at the satellite transmitting the signal (if needed), obtaining signal tracking and satellite position and time for three or more additional signals, and then calculating PVT using the estimates of signal timing and frequency along with positions and times at the satellites. Even though coarse initial synchronization is only one part of acquisition processing, this paper complies with common terminology, calling the circuit that performs coarse initial synchronization an “acquisition circuit.” Typically, an acquisition circuit crosscorrelates a locally generated signal replica against the received waveform containing multiple signals, interference and possibly jamming, and noise. In concept, the locally generated reference is shifted in time and frequency, forming a segment of a cross ambiguity function (CAF) [4] between the replica and the desired received signal. The time duration of the signal segments used in the crosscorrelation is called the coherent integration time. Noncoherent integration can be accomplished by adding the magnitudes of multiple CAFs, computed over the same ITU and IFU. This noncoherent integration enhances performance in noise and jamming, but consumes additional time to collect and process the longer segment of received waveform. Digital processing actually searches discrete values in time and frequency space, called time-frequency cells. The time span and frequency span searched in parallel by an acquisition circuit may be called a time-frequency tile—composed of multiple cells in a rectangular array. If the ITU or IFU is larger than the span of the tile, sequential tiles are computed serially to compute the CAF over the entire ITU and IFU. Figure 1 shows how cells and tiles fit into the ITU and IFU. Although for signals with short periodic spreading sequences, the largest ITU that must be searched corresponds to the period of the spreading sequence, signals whose spreading sequences have much longer periods require search of the entire ITU. Figure 1. Time-Frequency Tiles Filled with Cells Are Used to Search a Region of Initial Time Uncertainty and Initial Frequency Uncertainty The magnitude CAF, computed with or without noncoherent integration, is used to form a test statistic. A threshold setting algorithm establishes a criterion, and the time and frequency of any magnitude-squared CAF value that exceeds this threshold criterion correspond to a possible coarse initial synchronization. Some of these detection reports may be false, since establishing the threshold value too high excessively reduces the probability of a valid detection. Thus, some of the reported detections correspond to false initial synchronization points, and various techniques are used to distinguish between valid and false synchronization points. If spacing between time-frequency cells is too wide, a peak in the CAF signifying coarse initial synchronization may occur in between sample points, degrading the opportunity to detect this peak. In general, modulations having narrower peaks must be sampled faster to avoid this problem in the time domain. Sampling in the frequency domain is independent of modulation design, but instead is proportional to the reciprocal of the coherent integration time used in computing CAFs— longer coherent integration times require finer frequency spacing. When custom hardware is used for size and power efficiency, crosscorrelations are often implemented in the time domain, since two or fewer bits of quantization are needed, and less silicon area is needed. When the crosscorrelations used to compute the CAF are implemented using time-domain computations, the number of arithmetic operations required to compute a CAF that covers a given ITU increases with the square of the sampling rate. Thus, for signals whose modulation is binary phase shift keying with rectangular spreading symbols, the computational burden (quantified as the rate of arithmetic operations) increases with the square of the spreading code rate. Since the correlation peak is very narrow for signals with binary offset carrier (BOC) modulation, the same logic would motivate even higher sampling rates, and thus higher computational burdens, particularly when the subcarrier frequency is greater than the spreading symbol rate. Fortunately, sideband acquisition processing of BOC modulations [5] significantly reduces the computational burden for signals having BOC modulations with subcarrier frequency greater than the spreading code rate. Since the signal spectrum has distinct upper and lower sidebands, they can be separately filtered, downconverted to DC, and decimated at a sample rate commensurate with the spreading code rate, independent of the subcarrier frequency. Separate CAFs can be formed from the resulting waveforms from the upper and lower sidebands, using as a replica signal the spreading sequence without subcarrier modulation. The CAFs from upper and lower sidebands are noncoherently integrated. Figure 2 shows a conceptual block diagram of this processing for the M-code signal. The computational advantages from processing for coarse initial synchronization are significant. For M-code signal, sideband acquisition processing requires approximately 4% of the computational load required by wideband acquisition processing of the M code signal, and 50% of the computational load required by acquisition processing of the Y-code signal using the same coherent integration time and the same number of noncoherent integrations to search the same ITU and IFU. Storage requirements for sideband acquisition processing of the M-code signal are also significantly less than those for either wideband acquisition processing of the M-code signal, or acquisition processing of the Y-code signal.